The present invention generally relates to a microwave integrated circuit, and more particularly relates to a microstrip line structure for a semiconductor device operable at radio frequencies, which contributes to downsizing and performance enhancement of mobile communications unit terminals.
In recent years, the applications of mobile communications terminals of various types, including cellular phones and portable communications terminals, have been spanning a wider and wider range over the world. In Japan, cellular phones, operating on 900 MHz and 1.5 GHz bands, and personal handy phone systems (PHS), operating on 1.9 GHz band, have been popularized. Globally speaking, European GSM and DECT phones and American PCs phones are very popular.
Among these numerous types of mobile communications unit terminals, portable communications terminals, in particular, are required to be as small in size and as light in weight as possible. Thus, first of all, components for a portable communications terminal should have its size reduced and its performance enhanced. For example, to downsize a power amplifier for use in a radio-frequency transmitter for a portable communications terminal (hereinafter, simply referred to as an xe2x80x9cRF power amplifierxe2x80x9d), it is strongly needed to implement the RF power amplifier as a monolithic microwave IC (MMIC) of GaAs. In an MMIC, active components, matching circuit and bias supply are all integrated on a single chip. Thus, an MMIC can more effectively contribute to downsizing than a hybrid IC (HIC), in which matching circuit and bias supply are implemented as discrete chip components.
From a viewpoint of performance enhancement, however, an MMIC is said to be inferior to an HIC. This is because if an RF power amplifier is implemented as an MMIC, for instance, then parasitic resistive components, such as interconnection resistance, which are involved with semiconductor device processing for fabricating the MMIC, adversely increase, thus causing a considerable loss of the power to be transmitted. For that reason, a power amplifier implemented as an MMIC often results in lower power gain, lower power amplification and deteriorated distortion characteristic compared to a power amplifier implemented as an HIC. Thus, according to the currently available techniques, it is determined based on a necessary trade-off between downsizing and performance enhancement which part of a power amplifier should be implemented as an MMIC.
Hereinafter, an exemplary MMIC implementation of output matching circuit and drain-biasing circuit will be described with reference to FIGS. 10 through 15. An exemplary microstrip line structure will also be described with reference to FIG. 16. A microstrip line structure is a basic structure of a spiral inductor used as a passive component in the out-put matching circuit and drain-biasing circuit.
FIG. 10 illustrates a planar pattern for a final-stage MESFET and an output matching circuit thereof used for a high-output power amplifier transmitting a power of about 1 W. Following is respective parameters of the final-stage MESFET.
Unit finger length: 300 xcexcm
Total gate width: 24 mm
Frequency: 900 MHz
Power supply voltage: 3.5 V
Saturated output power with idle current of 400 mA supplied: about 1.5 W
Operating current: about 550 mA
Gain: about 12 dB
The gate of the MESFET 410 is connected to a gate-biasing pad 412 via a gate electrode extended line 411. The source of the MESFET 410 is connected to an MIM capacitor 409 via a source pad 413. The drain of the MESFET 410 is connected to a drain-biasing pad 415 via a drain extended line 414. One terminal of a spiral inductor 408 is connected to a part of the drain extended line 414, while the other terminal thereof is connected to an output pad 416 via the MIM capacitor 409.
The line of the spiral inductor 408 is made of gold plated to be about 3 xcexcm thick. The extended lines thereof are formed by evaporating and depositing titanium and gold thereon. The upper-layer conductor of the MIM capacitor 409 is made of gold plated, while the lower-layer conductor thereof is formed by evaporating and depositing titanium and gold thereon. The interlayer dielectric film of the capacitor 409 is formed by depositing silicon nitride (SiNx) with a dielectric constant of about 7 by a CVD process.
In the MMIC including the output matching circuit, the final-stage MESFET operates at a frequency of 900 MHz with a current of about 560 mA supplied. The MESFET provides a saturated output power of about 1.0 W with a power supply voltage of 3.5 V applied, and shows a gain of about 10 dB.
FIG. 11 illustrates an equivalent circuit of the MESFET and output matching circuit thereof shown in FIG. 10. A MESFET shown in FIG. 11, including gate 302, source 303 and drain terminals 304, corresponds to the MESFET 410 shown in FIG. 10. Equivalent series inductor 305, equivalent series resistor 306 and equivalent parallel capacitor 307 are connected to the drain terminal 304 of the MESFET. The equivalent series inductor 305 and resistor 306 form an equivalent circuit of the spiral inductor 408. In this example, the inductance value of the equivalent series inductor 305 is about 2.5 nH, the resistance value of the equivalent series resistor 306 is about 4 xcexa9 and the capacitance value of the equivalent parallel capacitor 307 is about 12 pF. The equivalent parallel capacitor 307 corresponds to the MIM capacitor 409 shown in FIG. 10.
FIG. 12 illustrates a location of load impedance ZL 301 of the MESFET on a Smith chart showing impedance matching from a 50xcexa9 line. The load impedance ZL 301 can be impedance-matched with the center of the Smith chart at 50xcexa9 by tracing paths formed by the parallel capacitive components and series inductive components. In this case, the value of the load impedance ZL 301 is 7xcexa9+j4 xcexa9.
Next, a drain-biasing circuit and a MESFET, in which a drain choking inductor is implemented as a part of an MMIC, will be described with reference to FIG. 13. The choking inductor is a device used for preventing radio frequency power from leaking to the drain power supply.
Following is respective parameters of the MESFET.
Unit finger length: 100 xcexcm
Total gate width: 1 mm
Frequency: 900 MHz
Power supply voltage: 3.5 V
Saturated output power with idle current of 20 mA supplied: about 120 mW
Operating current: about 23 mA
Gain: about 13 dB
The gate of the MESFET 505 is connected to a gate-biasing pad 507 via a gate electrode extended line 506. The source of the MESFET 505 is connected to a source pad 508. The drain of the MESFET 505 is connected to a drain extended line 509. Part of the drain extended line 509 is connected to a drain-biasing pad 510 via a spiral inductor 504.
In the MMIC including the drain choking inductor, the MESFET operates at a frequency of 900 MHz and with a power supply voltage of 3.5 V applied and a current of about 19 mA supplied. The MESFET provides a saturated output power of about 90 mW with an idle current of 20 mA supplied, and shows a gain of about 11 dB.
The line of the spiral inductor 504 is made of gold plated to be about 3 xcexcm thick. The extended lines thereof are formed by evaporating and depositing titanium and gold thereon.
FIG. 14 illustrates an equivalent circuit of the MESFET 505 and the drain-biasing circuit shown in FIG. 13. An equivalent series inductor 502 and an equivalent series resistor 503 constitute an equivalent circuit of the spiral inductor 504 shown in FIG. 13. In this example, the inductance value of the equivalent series inductor L 502 is 21 nH and the resistance value of the equivalent series resistor R 503 is 7.5 xcexa9.
FIG. 15 illustrates the location of choke impedance Zc 501 on a Smith chart. The choke impedance is located at a drain terminal of the MESFET, which is short-circuited at an end through which a drain voltage is applied. Usually, the choke impedance Zc 501 is ideally defined to be open. But since the choke impedance is sometimes used as a matching circuit in practice, the choke impedance is not necessarily open. In the example shown in FIG. 15, the choke impedance Zc 501 is located at an angle of phase rotation of about 140 degrees. FIG.
FIG. 16 illustrates the cross section of a microstrip line structure, which is a basic structure of a spiral inductor. As described above, a spiral inductor is used as a passive component for an output matching circuit or a drain-biasing circuit. Such a line structure includes: a line 602 formed on the surface of a GaAs substrate 601; and a grounded conductor 603 formed on the back of the GaAs substrate 601. The line 602 may be made of gold plated to be about 3 xcexcm thick, for example.
In the first prior art example illustrated in FIGS. 10 through 12, the output impedance of the final-stage GaAs FET used as a power amplifier is as low as about 10 xcexa9 or less. Accordingly, the resistive components of the output matching circuit, including the interconnection resistance of the spiral inductor formed on the GaAs substrate, increases the power lost by the output matching circuit. As a result, the power amplifier shows lower gain, lower power amplification (corresponding to operating current) and deteriorated distortion characteristic. In order to avoid problems such as these, the thickness or width of a line may be increased. However, the thickness of a line cannot exceed a certain upper limit defined by various restrictions on semiconductor device processing. Also, the wider a line, the larger the area occupied by the line on a chip, which is contradictory to the demand of downsizing.
Even in a medium-output power amplifier transmitting a power of about 100 W, the input, interstage and output matching circuits thereof are included in an MMIC. In such a case, the output matching circuit is built in an MMIC, in which the output impedance of a final-stage GaAs FET used for the power amplifier is as high as approximately 300xcexa9 or more. Even so, the resistive components of the output matching circuit, including the interconnection resistance of the spiral inductor formed on the GaAs substrate, increases the power lost by the output matching circuit, thus adversely affecting the performance thereof.
In the second prior art example shown in FIGS. 13 through 15, since the drain-biasing circuit is implemented as a part of an MMIC, the choking spiral inductor occupies a larger area on a GaAs substrate, thus increasing the area of the MMIC chip and interfering with downsizing. Furthermore, a drain voltage externally applied drops due to the parasitic resistance of the spiral inductor line, resulting in deterioration in performance of the power amplifier. Accordingly, the second prior art example cannot make full use of the essential characteristics of the power amplifier, and cannot sufficiently contribute to the performance enhancement thereof.
An object of the present invention is providing a semiconductor device operable at radio frequencies, which can contribute to both downsizing and performance enhancement of mobile communications terminals.
A semiconductor device according to the present invention has a line structure formed on a semiconductor substrate. The line structure includes: a conductor layer formed on the semiconductor substrate; a dielectric film formed on the conductor layer; and a conductor line formed on the dielectric film. The dielectric film includes: a first dielectric portion, at least part of the first dielectric portion being located between the lower surface of the conductor line and the upper surface of the conductor layer; and second and third dielectric portions laterally arranged to interpose the first dielectric portion therebetween. The dielectric constant of the first dielectric portion is different from at least one of the dielectric constants of the second and third dielectric portions.
In one embodiment of the present invention, the dielectric constant of the first dielectric portion may be lower than those of the second and third dielectric portions.
In another embodiment of the present invention, at least one of the dielectric constants of the second and third dielectric portions may be higher than 10.
In still another embodiment, the device may further include another dielectric film covering the conductor line.
Another semiconductor device according to the present invention also has a line structure formed on a semiconductor substrate. The line structure includes: a conductor layer formed on the semiconductor substrate; a dielectric film formed on the conductor layer; and a conductor line formed on the dielectric film. The dielectric film includes two or more dielectric layers with mutually different dielectric constants.
In one embodiment of the present invention, at least one of the two or more dielectric layers may include: a first dielectric portion, at least part of the first dielectric portion being located between the lower surface of the conductor line and the upper surface of the conductor layer; and second and third dielectric portions laterally arranged to interpose the first dielectric portion therebetween. The dielectric constant of the first dielectric portion may be different from at least one of the dielectric constants of the second and third dielectric portions.
In another embodiment of the present invention, at least one of the two or more dielectric layers has preferably been patterned.
Still another semiconductor device according to the present invention also has a line structure formed on a semiconductor substrate. The line structure includes: a conductor layer formed on the semiconductor substrate; a first dielectric film formed on the conductor layer; a conductor line formed on the first dielectric film; and a second dielectric film covering the conductor line.
In one embodiment of the present invention, the first dielectric film may include two or more dielectric layers with mutually different dielectric constants.
Yet another semiconductor device according to the present invention also has a line structure formed on a semiconductor substrate. The line structure includes: a conductor layer formed on the semiconductor substrate; a dielectric film formed on the conductor layer; and a conductor line formed on the dielectric film. A region of the conductor layer, which is located under the conductor line, has been removed at least partially.
In one embodiment of the present invention, the dielectric film may include two or more dielectric layers with mutually different dielectric constants.
In another embodiment of the present invention, the device may further include a second dielectric film covering the conductor line.
In still another embodiment, the dielectric constant of the second dielectric film may be higher than 10.
Yet another semiconductor device according to the present invention also has a line structure formed on a semiconductor substrate. The line structure includes: a coplanar conductor layer formed over the semiconductor substrate; and a dielectric film formed on the coplanar conductor layer. The coplanar conductor layer includes: a grounded conductor layer; and a conductor line spaced apart from the grounded conductor layer. The dielectric constant of the dielectric film is higher than 10.
In one embodiment of the present invention, a dielectric with a dielectric constant equal to or smaller than 10 may exist between the grounded conductor layer and the conductor line.
Yet another semiconductor device according to the present invention also has a line structure formed on a semiconductor substrate. The line structure includes: a first dielectric film formed on the semiconductor substrate; a coplanar conductor layer formed on the first dielectric film; and a second dielectric film formed on the coplanar conductor layer.
In one embodiment of the present invention, the dielectric constant of at least one of the first and second dielectric films may be higher than 10.
In another embodiment of the present invention, the first dielectric film may include two or more dielectric layers with mutually different dielectric constants.
In still another embodiment, the device may further include an active component operable at radio frequencies, the active component being formed on the semiconductor substrate and electrically connected to the line structure.
According to the present invention, the equivalent dielectric constant of a dielectric film can be optimized. In addition, the line length of a spiral inductor, which is required for matching the impedance of an active component with a desired load impedance or attaining a desired choke inductance, can be shortened, thus reducing the parasitic resistive components involved with the spiral inductor. As a result, it is possible to provide a semiconductor device operable at radio frequencies and contributing to both downsizing and performance enhancement of mobile communications unit terminals.